There is a considerable interest around the world in growing GaN on silicon (Si) wafer for light emitting diodes (LEDs) and power devices. However, the heterogrowth process for forming GaN on Si wafer presents the same stress problems that have been faced with silicon carbide (SiC) on Si.
It has been demonstrated by the “Anvil Grid” process that the use of a silicon dioxide (SiO2) grid between die which is destroyed during the temperature ramp to the growth temperature (Carbonisation) produces a growth in these grid regions of polycrystalline SiC. This produces a low stress region between the monocrystalline SiC die which inevitably contain a tensile stress. In this way stresses are developed across die dimensions rather than the whole wafer diameter and the wafer bow is reduced.
It is an aim of the present invention to reduce wafer bow when GaN is formed on a SiC wafer.